Sam H. Noh

Sam H. Noh

Ulsan National Institute of Science and Technology

Professor

Department of Computer Science and Engineering

Graduate School of Artificial Intelligence

Research Area

  • #Computer science
  • #Operating system
  • #Parallel computing
  • #Cache
  • #Flash memory
  • #Cache algorithms
  • #Memory map
  • #Interleaved memory
  • #Memory management
  • #Semiconductor memory

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Contact information

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Related papers to
‘ Computer science ‘ : 11

  • CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures

    2014/09

    1.7 Impact Factor

    132 citations

    Soyoon Lee, Hyokyung Bahn, Sam H. Noh

    DOI : 10.1109/TC.2013.98

    • #Computer science
    • #Parallel computing
    • #Semiconductor memory
    • #Overlay
    • #Dram
    • #Random access memory
    • #Sense amplifier
    • #Computer memory
    • #Memory management
    • #Registered memory
    • #Memory controller
    • #Memory architecture
    • #Phase-change memory
    • #Memory hierarchy
    • #Write combining
    • #Locality of reference
    • #Memory refresh
    • #Memory map
    • #Interleaved memory
    • #Flat memory model
    • #Uniform memory access
    • #Dram memory
    • #Virtual memory
    • #Non-volatile random-access memory
    • #Cache-only memory architecture
    • #Write buffer
    • #Conventional memory
    • #Memory rank
    • #Page replacement algorithm

All papers authored by
‘ Sam H. Noh ’ : 11

  • CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures

    2014/09
    IEEE TRANSACTIONS ON COMPUTERS

    1.7 Impact Factor

    132 citations

    Soyoon Lee, Hyokyung Bahn, Sam H. Noh

    DOI : 10.1109/TC.2013.98

    • #Computer science
    • #Parallel computing
    • #Semiconductor memory
    • #Overlay
    • #Dram
    • #Random access memory
    • #Sense amplifier
    • #Computer memory
    • #Memory management
    • #Registered memory
    • #Memory controller
    • #Memory architecture
    • #Phase-change memory
    • #Memory hierarchy
    • #Write combining
    • #Locality of reference
    • #Memory refresh
    • #Memory map
    • #Interleaved memory
    • #Flat memory model
    • #Uniform memory access
    • #Dram memory
    • #Virtual memory
    • #Non-volatile random-access memory
    • #Cache-only memory architecture
    • #Write buffer
    • #Conventional memory
    • #Memory rank
    • #Page replacement algorithm

Related papers to
‘ Computer science ‘ : 11

  • CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures

    2014/09
    IEEE TRANSACTIONS ON COMPUTERS

    1.7 Impact Factor

    132 citations

    Soyoon Lee, Hyokyung Bahn, Sam H. Noh

    DOI : 10.1109/TC.2013.98

    • #Computer science
    • #Parallel computing
    • #Semiconductor memory
    • #Overlay
    • #Dram
    • #Random access memory
    • #Sense amplifier
    • #Computer memory
    • #Memory management
    • #Registered memory
    • #Memory controller
    • #Memory architecture
    • #Phase-change memory
    • #Memory hierarchy
    • #Write combining
    • #Locality of reference
    • #Memory refresh
    • #Memory map
    • #Interleaved memory
    • #Flat memory model
    • #Uniform memory access
    • #Dram memory
    • #Virtual memory
    • #Non-volatile random-access memory
    • #Cache-only memory architecture
    • #Write buffer
    • #Conventional memory
    • #Memory rank
    • #Page replacement algorithm
  • Chip-Level RAID with Flexible Stripe Size and Parity Placement for Enhanced SSD Reliability

    2016/04
    IEEE TRANSACTIONS ON COMPUTERS

    2.9 Impact Factor

    29 citations

    Jaeho Kim, Eunjae Lee, Jongmoo Choi, Donghee Lee, Sam H. Noh

    DOI : 10.1109/TC.2014.2375179

    • #Computer science
    • #Computer hardware
    • #Chip
    • #Flash memory
    • #RAID
    • #Data striping
    • #Bit error rate
    • #Standard RAID levels
    • #Parity drive
    • #Nested RAID levels

Get access to
Contact information

Log in

All papers authored by
‘ Sam H. Noh ’ : 11

  • CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures

    2014/09
    IEEE TRANSACTIONS ON COMPUTERS

    1.7 Impact Factor

    132 citations

    Soyoon Lee, Hyokyung Bahn, Sam H. Noh

    DOI : 10.1109/TC.2013.98

    • #Computer science
    • #Parallel computing
    • #Semiconductor memory
    • #Overlay
    • #Dram
    • #Random access memory
    • #Sense amplifier
    • #Computer memory
    • #Memory management
    • #Registered memory
    • #Memory controller
    • #Memory architecture
    • #Phase-change memory
    • #Memory hierarchy
    • #Write combining
    • #Locality of reference
    • #Memory refresh
    • #Memory map
    • #Interleaved memory
    • #Flat memory model
    • #Uniform memory access
    • #Dram memory
    • #Virtual memory
    • #Non-volatile random-access memory
    • #Cache-only memory architecture
    • #Write buffer
    • #Conventional memory
    • #Memory rank
    • #Page replacement algorithm
  • Chip-Level RAID with Flexible Stripe Size and Parity Placement for Enhanced SSD Reliability

    2016/04
    IEEE TRANSACTIONS ON COMPUTERS

    2.9 Impact Factor

    29 citations

    Jaeho Kim, Eunjae Lee, Jongmoo Choi, Donghee Lee, Sam H. Noh

    DOI : 10.1109/TC.2014.2375179

    • #Computer science
    • #Computer hardware
    • #Chip
    • #Flash memory
    • #RAID
    • #Data striping
    • #Bit error rate
    • #Standard RAID levels
    • #Parity drive
    • #Nested RAID levels

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